Monday, August 03, 2009

Idea #31 Web-based Hardware Design From C To Silicon

Hardware design should not be a black art any more, no need to master Verilog or VHDL. Design flow and tools have matured enough that, unless you are doing cutting-edge micro-processors or wireless chips inside the iPhone, you can get your chip design done fairly easily.

To enable open source silicon and wide adoption of hardware design, we need an online design tools, starting from the mostly widely used programming language, C.

Quite a few software vendors have started offering C-synthesis tools, from industry observer John Cooley.

Here's an idea for a business model to make the online tool work.

You may enter a piece of C code from the web interface. Push a button will get you the equivalent gate-level netlist that implements the same functionality. In addition, performance analysis reports, such as, how much speed up will be gained by implementing in silicon versus software, methods to interface with other modules of the system, etc.

All these are free, except when you want to use the netlist in hardware, whether in terms of FPGA (field programmable logic arrays) or ASIC (application specific integrated circuit), a license fee needs to be paid, based on the size and scale of the system.

With an easy-to-use interface, it enables more system designers to explore the option of instantiating customized hardware.

The long tail of hardware design.

photo credit BotheredByBees


  1. Anonymous4:01 AM

    A few months ago I found a company that was already doing this already.

    There are a host of problems with the solution though. First, you have to be willing to upload your confidential design to a 3rd party server. Most companies I know won't allow that -- but smaller ones could. Second, the high level synthesis provider would need to have the ancillary tools available as well.

    High level synthesis is hardly a push button process. Most of the time the C is software code that is not suitable for hardware implementation. While I think the concept is correct I believe it will be some time before it is practical.

  2. Good comments. Appreciated.

    On confidentiality, most companies that I know of already use to store sensitive customer information, bug tracking, even organization structure. Not allowing that few lines of C/VHDL/Verilog? Doesn't make sense. It's a culture issue IMO.

    Loading the huge LEF/DEF files is indeed a concern.

    On usability, agree, the whole design flow is more than a push button, especially when timing/clock constraints, floorplan irregularities, etc. are all mingled in the iterative flow.

    However for software module speedup like what Microsoft is doing, on FPGA or even CUDA, you can get push button qualitative results.